Adiabatic Switching and Power Dissipation of Dynamic Resonant Tunneling Device Logic Circuits
نویسندگان
چکیده
Dynamic power dissipation is an important aspect of resonant tunneling device circuit design, especially if clock frequencies beyond 1 GHz are intended. In this paper we investigate the different sources of power dissipation of a dynamic resonant tunneling device logic family. Due to the self-latching behavior of the gates and the bitlevel pipelined circuit style an adiabatic clocking scheme is ideally suited to reduce the dynamic switching energy. Extrapolations for laterally scaled resonant tunneling devices predict a total power dissipation below 20 μW per gate at 5 GHz for a minimum feature size of 200 nm and a peak current density of jP = 10 kA=cm2. Compared to a non-adiabatic operation this is a reduction of the switching energy by about one order of magnitude.
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